1. Field of the Invention
The present invention generally relates to delay time estimation methods for estimating a delay time in a logic circuit composed of transistors and to recording mediums in which a computer program for executing a delay time estimation method is stored. More particularly, the present invention relates to a delay-time estimation method and a recording medium storing an estimation program with which efficient and precise estimation of delay time is possible.
2. Description of the Related Art
The necessity for accurate signal analysis in a logic circuit is growing for designers of high-speed large-scale LSIs. Signal delay is one of the most important parameters because it is important for an LSI designer to know a timing margin in order to determine whether an LSI can operate properly. Methods for modeling and estimating time delay have been proposed.
FIGS. 9 through 11 show a processing flow for delay time estimation according to the related art. Referring to FIG. 9, the related-art delay estimation includes extraction of information relating to connection of the target circuit from a layout. The extracted circuit is modeled as a series comprising inverters (INV) 101 and 102 connected via a wire 103. Based on this circuit connection information, circuit configuration information in which a load is modeled by an RC component is produced, as shown in FIG. 10. A source model 106 corresponding to the inverter 101 is modeled by a combination of a power source 104 and resistance 105. A load component 108 comprises an RC distributed constant circuit 107 corresponding to the wire 103, and input pin capacitance Cg corresponding to the inverter 102, the RC distributed constant circuit 107 and the capacitance Cg being determined so that the admittance downstream from an output terminal of the gate provides a match with a third-order approximation.
The resistance and capacitance constituting the load component 108 is approximated by a finite number of RC components. The input capacitance of the RC distributed constant circuit 107 is modeled by capacitance C2. The combined output capacitance of the RC distributed constant circuit 107 and input pin capacitance Cg of the inverter 102 is modeled by capacitance C1. The capacitance C1, capacitance C2 and resistance R of the RC distributed constant circuit 107 form a π-load model 109 as shown in FIG. 11.
The π-load model, formed by two C components and one R component, is constructed such that, for any type of source model 106, a voltage waveform, occurring at the output terminal of the gate when the circuit of FIG. 10 is established, is approximated by a voltage waveform obtained as a result of analyzing the circuit of FIG. 11.
The approximation described above is disclosed in Peter R. O'Brien and Thomas L. Savarino, Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation, Proc. IEEE International Conference on Computer-Aided Design, 1989. Admittance Y(s) looking downstream from the gate output terminal is estimated (FIG. 3, equations (19)–(32)). The admittance Y(s) thus obtained is used to estimate R, C1 and C2 (equations (14)–(16)).
The load model 109 is then connected to the source model 106 so as to estimate a delay time through response analysis. The voltage level of the power source 104 and the resistance 105 have respective values determined by modeling conditions. The method of computing the voltage level and resistance is described in details in Florentin Dartu, Noel Menezes, Jessica Qian, and Lawrence T. Pillage, A Gate-Delay Model for High-Speed CMOS Circuits, Proc. 31st ACM/IEEE Design Automation Conference, 1994, so that a detailed description is omitted.
A description will now be given of the operation according to the related art.
FIG. 12 shows a construction of the inverter 101 comprising a PMOS transistor and an NMOS transistor. In a rising transition at the output terminal Y, as the potential at the input terminal A goes from a high level (H) to a low level (L), the PMOS transistor P1 makes a transition from an OFF state to an ON state so as to charge an output load. When a decrease in the potential between the source and drain of the PMOS transistor P1 is relatively bigger than the magnitude of change in the gate potential, a transition from a region, characterized by an increase in a current with time, to another region characterized by a rapid exponential decrease in the current occurs (see pattern 2 of FIG. 5). Referring to FIG. 13, in the related-art source model 106, an internal voltage source E(t), whose voltage level shows a linear variation between 0 and Vdd in a time Δt, is used to represent the transition described above.
According to the related art, the π-load model 109 shown in FIG. 11 subject to delay estimation is approximated by a purely capacitive load model as shown in FIG. 14 providing an equivalent response. In this case, equivalent capacitance is determined by considering the shielding effect provided by the resistance R constituting the π-load model 109. A delay time is determined by searching a table listing delay time along with gradients of predetermined input waveforms and output load capacitance. The table is searched so that a delay time that matches the modeling condition is determined by interpolation.
The related-art delay time estimation has a disadvantage in that it is not adapted for another possible transition pattern (pattern 1 of FIG. 5) in which there is a transition from a first region, characterized by an increase in current with time, to a second region, characterized by a gradual decrease in current, and then to a third region, characterized by an exponential decrease. The related-art internal power source model E(t) as shown in FIG. 13, characterized by a linear variation between 0 and Vdd in a time Δt, fails to represent a saturation region in which the current gradually decreases (region 2 of FIG. 5). Therefore, the related-art method fails to provide delay time estimation that matches the operating characteristic of transistors.
Another disadvantage of the related art is that there is a need for a library of two-dimensional delay tables listing gradients of input waveforms and output load capacitance, thus making it necessary to store a large volume of data. Interpolation errors are incurred as a result of using the tables. If the π-load model is to be used instead of the purely capacitive model, the dimension of the table increases so that the volume of data is increased, thereby rendering its implementation impossible. The practice of conversion into equivalent capacitance, performed in this background, generates errors.